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(R)
ISL6206
Data Sheet May 2002 FN9071.1
High Voltage Synchronous Rectified Buck MOSFET Driver
The ISL6206 is a high voltage, high frequency, dual MOSFET driver specifically designed to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter topology in mobile computing applications. This driver combined with an Intersil Multi-Phase Buck PWM controller forms a complete single-stage core-voltage regulator solution for advanced mobile microprocessors. The ISL6206 features a three-state PWM input that, working together with any Intersil multiphase PWM controllers, will prevent a negative transient on the output voltage when the output is being shut down. This feature eliminates the Schottky diode that is usually seen in a microprocessor power system for protecting the microprocessor from reversed-output-voltage damage. The output drivers in the ISL6206 has the capacity to efficiently switch power MOSFETs at frequencies up to 2MHz. Each driver is capable of driving a 3000pF load with a 15ns propagation delay and 20ns transition time. This product implements bootstrapping on the upper gate, reducing implementation complexity and allowing the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously.
Features
* Drives Two N-Channel MOSFETs * Adaptive Shoot-Through Protection * 30V Operation Voltage * Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 15ns * Three-state Input for Output Stage Shutdown * Internal Bootstrap Schottky Diode
Applications
* Core Voltage Supplies for Intel and AMD(R) Mobile Microprocessors * High Frequency Low Profile DC-DC Converters * High Current Low Output Voltage DC-DC Converters * High Input Voltage DC-DC Converters
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Pinout
ISL6206CB (SOIC) TOP VIEW
UGATE 1 2 3 4 8 7 6 5 PHASE NC VCC LGATE
Ordering Information
PART NUMBER ISL6206CB ISL6206CB-T TEMP. RANGE (oC) -10 to 85 PACKAGE 8 Ld SOIC PKG. NO.
BOOT
M8.15
PWM GND
8 Ld SOIC Tape and Reel
ti
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved AMD(R) is a registered trademark of Advanced Micro Devices, Inc.
ISL6206 Block Diagram
ISL6206
VCC BOOT UGATE VCC 10K PWM 10K
SHOOTTHROUGH PROTECTION
PHASE
CONTROL LOGIC
VCC LGATE GND
Typical Application - Two Phase Converter Using ISL6206 Gate Drivers
VBAT +5V +5V +5V VCC FB VCC VSEN PWM1 PGOOD PWM2 NC MAIN CONTROL LGATE PWM DRIVE ISL6206 PHASE COMP BOOT UGATE +VCORE
VID
ISEN1 ISEN2 +5V VCC FS DACOUT GND PWM DRIVE ISL6206 NC PHASE VBAT
BOOT UGATE
LGATE
2
ISL6206
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V BOOT Voltage (VBOOT). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 36V Phase Voltage (VPHASE) (Note 1) . . . VBOOT - 7V to VBOOT + 0.3V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 125oC
Thermal Information
Thermal Resistance JA (oC/W) SOIC Package (Note 2) . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -10oC to 85oC Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125oC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The Phase Voltage is capable of withstanding -7V when the BOOT pin is shorted to GND. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications PARAMETER VCC SUPPLY CURRENT Bias Supply Current PWM INPUT Input Current PWM three-state Rising Threshold PWM three-state Falling Threshold three-state Shutdown Holdoff Time SWITCHING TIME UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay OUTPUT Upper Drive Source Resistance Upper Driver Source Current (Note 3) Upper Drive Sink Resistance Upper Driver Sink Current (Note 3) Lower Drive Source Resistance Lower Driver Source Current (Note 3) Lower Drive Sink Resistance Lower Driver Sink Current (Note 3) NOTE: 3. Guaranteed by design, not tested. RUGATE IUGATE RUGATE IUGATE RLGATE ILGATE RLGATE ILGATE 500mA Source Current VUGATE-PHASE = 2.5V 500mA Sink Current VUGATE-PHASE = 2.5V 500mA Source Current VLGATE = 2.5V 500mA Sink Current VLGATE = 2.5V 3.1 700 1.5 1.1 3.1 700 1.5 1.1 5.0 2.6 5.0 2.6 mA A mA A tRUGATE tRLGATE tFUGATE tFLGATE tPDLUGATE tPDLLGATE VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load 20 20 15 15 15 15 ns ns ns ns ns ns IPWM VPWM = 5V VPWM = 0V VVCC = 5V VVCC = 5V VVCC = 5V, Temperature = 25 C 3.3 250 -250 300 1.7 A A V V ns IVCC PWM pin floating, VVCC = 5V 30 A Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
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ISL6206 Functional Pin Description
UGATE (Pin 1)
Upper gate drive output. Connect to the gate of the high-side N-Channel power MOSFET.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Bootstrap Diode and Capacitor section under DESCRIPTION for guidance in choosing the appropriate capacitor value.
Description
Operation
The ISL6206 dual MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLLGATE], the lower gate begins to fall. Typical fall times [tFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [tPDHUGATE] based on how quickly the LGATE voltage drops below 1V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shootthrough. Once this delay period is complete the upper gate drive begins to rise [tRUGATE] and the upper MOSFET turns on. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLUGATE] is encountered before the upper gate begins to fall [tFUGATE]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, tPDHLGATE. The upper MOSFET gate voltage is monitored and the lower gate is allowed to rise after the upper MOSFET gate-to-source voltage drops below 1V. The lower gate then rises [tRLGATE], turning on the lower MOSFET.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of any Intersil multiphase controllers.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to the gate of the low-side N-Channel power MOSFET.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND.
NC (Pin 7)
No connection. Leave this pin floating.
Timing Diagram
PWM
tPDHUGATE tPDLUGATE tRUGATE tFUGATE
UGATE
LGATE
tFLGATE tPDLLGATE tPDHLGATE
tRLGATE
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ISL6206
Three-state PWM Input
A unique feature of the ISL6206 and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled.
Power Dissipation
Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125oC. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The power dissipated by the driver is approximated as:
P = fsw ( 1.5V U Q + V L Q ) + I DDQ V U L CC
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the gate driver has turned off one MOSFET before the gate voltage of the other MOSFET is allowed to rise. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise.
where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is negligible
Bootstrap Diode and Capacitor
This driver features an internal Schottky bootstrap diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from the following equation:
Q GATE C BOOT ----------------------V BOOT
where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is 0.22F. A good quality ceramic capacitor is recommended.
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ISL6206 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6

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